In dynamic random-access memory (DRAM), die architecture may be changed to fit more memory into a smaller area. Some methods include re-orienting arrays in a die to achieve a layout that increases a number of arrays. However, because each array needs to receive control signals and to receive and provide data during memory access operations, the signal lines for these control signals and data may end up running through space occupied by another memory array, which may require an increase in die size to fit all required signal lines. Further, including independent access blocks for each array increases complexity, die size, and array access time. Lastly, because the signal lines run through (or above or below) other memory arrays, the signal lines become longer. The longer signal lines may increase a total resistance along the signal line, and may increase an amount of time for a memory operation beyond a desired maximum, for example, during a fast column to column decode cycle.